Erasable Programmable Read-only Memories (EPROMs), Electrically Erasable Programmable Read-only Memories (E.sup.2 PROMs), and Flash E.sup.2 PROMs (hereafter collectively, PROMs) have several structures which allow them to hold a charge without refresh for extended periods of time. FIG. 1 shows a top view of a PROM array, FIG. 2 shows a cross section along "AA" of FIG. 1, and FIG. 3 shows a cross section along "BB" of FIG. 1. The charge itself is stored on a "floating gate" 10 also referred to as Poly 1 or P1, which is a structure of polycrystalline silicon (hereafter, poly) surrounded on all sides by a layer of oxide 12. Located superjacent and parallel to this P1 structure is another poly structure, the "control gate" 14 or P2. P1 10 and P2 14 act as the two plates of a capacitor. Below the P1 layer are two N+ junctions, one which acts as the transistor source 16 and the other as the drain 18, which are doped into a P-type substrate 20. The portion of the substrate 20 between the source 16 and the drain 18 is the channel 22. The cell functions like an enhancement-type N-channel metal oxide semiconductor field effect transistor (MOSFET) with two gates of poly.
There are structures that make up a PROM array which are common to several transistors in the array. FIG. 1 shows the transistor sources 16, drains 18, digit lines 24, floating gates 10, and control or "word" lines 26 which form control gates 14 as they pass over the floating gates 10. Also shown as a dotted line is the "active area" 28 interspersed with areas of field oxide 30. A single word line 26 is common to all transistors in a single column acting as a control gate 14 for all transistors in the column. When the word line is selected it activates all transistors in the column. The source regions 16, which run parallel with the control lines 26, are common to all transistors in two adjacent columns. Individual transistor drains 18 are common to two transistors in adjacent columns. The digit (or bit) lines 24 are common with the drains 18 of all transistors in a single row.
The potential which must be applied on the control gate to turn on the transistor is much higher in a device storing a charge than in a device which does not have a potential stored on P1. To read the content of the floating gate, a potential somewhere between the low and high potential values (i.e. the threshold voltage V.sub.t) is applied to the control gate. If a cell is set to a zero, arbitrarily defined by storing -3 V on the floating gate 10, and 3.5 V is applied to the control gate, the net difference in potential which effects the transistor channel is not great enough to allow the electrons to pass from the source to the drain. Assuming a 0.7 coupling coefficient (described below) the effect on the transistor is defined as -3.0 V+(3.5 V.times.0.7)=-0.55 V. If V.sub.t is 1.0 V, the transistor will not trip. If a cell is set to a one, arbitrarily defined by storing 0 V on the floating gate 10, the 3.5 V difference between the control gate and the floating gate will affect the channel greatly enough to allow electrons to pass between the source and drain. Assuming the same 0.7 coupling coefficient, the effect on the transistor is defined as 0 V+(3.5 V.times.0.7)=2.45 V. After the control gate 26 is activated, each cell along that control gate 26 outputs the cell information on their respective digit lines 24, either an OFF if the floating gate is storing a -3.0 V or an ON if the cell is storing 0.0 V. The information on the digit line 24 which corresponds to the cell to be read is obtained with a sense amplifier (not shown), with one sense amp for each digit line.
In a conventional Flash E.sup.2 PROM cell, the floating gate and the control gate are both manufactured from N-type poly. The floating gate and control gate are both highly doped with N+ material. The substrate is P-type conductivity with N+ junctions which form the source and drain regions. To manufacture N-type poly, a poly structure is doped with atoms having more than four valence electrons (group V or higher), such as arsenic or phosphorus, which introduces negatively charged majority carriers into the silicon and make the semiconductive material much more conductive than nondoped poly due to electron conduction. To manufacture P-type poly, a poly structure is doped with atoms having less than four valence electrons (group III or lower), such as boron, which introduce positively charged majority carriers and make the semiconductive material more conductive than undoped poly due to hole conduction but less conductive than N-type doped poly. The majority charge carrier type is also referred to as conductivity type.
There are many ways to program a PROM. In one technique, a potential such as 12 V, for example, is applied on the control gate. Simultaneously, a voltage pulse, for example 8 V, is applied between source and drain. The large positive potential on the control gate establishes an electric field in the insulating oxide. This electric field attracts the electrons generated from the so-called "avalanche breakdown" of the transistor due to the high drain and control gate potentials, and accelerates them toward the floating gate, which they enter through the oxide dielectric. In this way the floating gate is charged, and the charge that accumulates on it becomes trapped.
The amount of electron flow is determined partly by the thickness of the gate oxide. If the gate oxide is very thin, the electron flow can be relatively large. In this case, a lower voltage can be applied on the drain and control gate. If the oxide is thicker, the electron flow is small and a large potential must be applied to the drain and control gate to influence the electrons to pass through the gate oxide to the floating gate.
Another programming method is by Fowler-Nordheim tunneling. By applying a high potential on the word line and grounding the source and/or the drain, electrons will tunnel through the thin gate oxide to the floating gate. Fowler-Nordheim tunneling is critically determined by the potential between the control gate and the source and/or drain (and therefore the electric field) and the thickness of the gate oxide.
To return the floating gate from a charged state to a state with no charge (erase), the electrons are caused to return to the substrate. In an EPROM, this is accomplished with ultraviolet light which excites the electrons past a certain energy state, thereby allowing them to pass through the oxide and return to the substrate. In an E.sup.2 PROM, this excitation is accomplished with an electrical field.
The floating gate of an E.sup.2 PROM forms a capacitor with the control gate, as described above, and also with the source, the drain, and the channel. This arrangement is described in FIG. 4. The coupling capacitances associated with P1 are described by the coupling coefficient, which is depicted by the equation (referring to FIG. 2): ##EQU1## where CC is the coupling coefficient, C1 represents the coupling between P1 and P2, C2 represents the coupling between P1 and the source, C3 represents the coupling between P1 and the drain, and C4 represents the coupling between P1 and the channel. As can be determined from the equation, the coupling coefficient can never reach the ideal state (1.00) since the capacitance between the floating gate and the control gate is always divided by itself plus some additional capacitance. Still, the goal of designers is to bring the coupling coefficient as close to unity as possible.
The coupling between the floating gate and the channel (C4 in the equation above) is partially determined by the thickness of the gate oxide under the floating gate. Thinning the oxide has various advantageous and detrimental effects on the functionality of the cell. With a relatively thin gate oxide, which can range from 100 .ANG. to 150 .ANG. with current technology, the cell requires less voltage to program. The thinner gate oxide allows an easier passage of the electrons from the source (or drain) region to the floating gate, thereby requiring less voltage to program the array. In addition to requiring less power, the programming of one cell does not as greatly affect an adjacent cell (less disturbance), and the data is more reliably written into the cell with the thinner gate oxide. Thinning the gate oxide, however, increases the capacitance between the floating gate and the substrate as the two "plates" of the capacitor are closer together. As seen in the equation above, this decreases the coupling coefficient. A thin gate oxide, while an aid in programming, adversely affects the storage of the charge on the floating gate for the same reason, that electrons can more easily pass through the gate oxide, and can therefore discharge from the floating gate to the substrate.
Conversely, a cell with a thicker gate oxide, for instance from about 150 .ANG. to 250 .ANG., has a larger distance between the two plates of the capacitor (the floating gate and the transistor channel region) and a coupling coefficient which isn't adversely affected by C4. This cell has a thicker tunneling dielectric, and therefore an excellent storage of the charge on the floating gate as the charge doesn't easily leak from the floating gate to the substrate through the thick gate oxide. However, it is difficult to program this cell, and programming requires a higher potential. This increases power consumption and the programming of one cell can adversely affect an adjacent cell.
Attempts have been made to create a cell with a large percentage of thick gate oxide under the floating gate for good storage of the charge, and an area under the floating gate having thin gate oxide to allow for low voltage programming. While a cell with these specifications functions effectively, attaining this structure reliably has proven to be difficult, especially with high density devices. A more easily manufacturable PROM cell having the advantages of both thick and thin gate oxide would be a desirable structure.